EPM5192AJI84-15 vs EPM5192AGC-15 Vergleich

Detaillierter Direktvergleich von EPM5192AJI84-15 von Altera und EPM5192AGC-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5192AJI84-15 EPM5192AGC-15
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $27,80 $27,80
Device Family MAX 5000 EPLD —
Product Type UV-Erasable / OTP Complex PLD EPLD (Erasable Programmable Logic Device)
Macrocells 192 192
Logic Array Blocks (LABs) 16 —
User I/O Pins 84 —
Propagation Delay (tPD) 15 ns 15 ns (pin-to-pin, -15 speed grade)
Supply Voltage (VCC) 4.5 V to 5.5 V (nominal 5 V) 5 V
Process Technology CMOS EPROM (UV-erasable) —
Package Type 84-pin JLCC (J-Leaded Ceramic Chip Carrier) with quartz window —
Montageart Through-Hole (SMD socket-compatible) —
Betriebstemperatur -40 °C to +85 °C (Industrial, 'I' suffix) [DATA_NEEDED: operating temperature range]
Programming Method UV erase + EPROM program via standard Altera programmer UV erase + EPROM program (via Altera programmer)
Design Tool Support MAX+PLUS II (legacy); not supported by modern Quartus Prime —
RoHS-Status unknown [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant]
Lead-Free unknown —
Halogenfrei unknown —
Functional Equivalent (Plastic OTP) EPM5192AJC84-15 (windowless plastic JLCC, same die) —
Series — MAX 5000
Logic Array Blocks — 16 (typical for 192-macrocell MAX 5000)
Maximum User I/O Pins — 64
Dedicated Inputs — 7
Total Inputs — 72
Technology — CMOS, UV-erasable EPROM
Gehäuse — Ceramic Pin Grid Array (PGA)
Lebenszyklusstatus — Obsolete / Last Time Buy (per Altera legacy product list)

Datenblätter & Ressourcen

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