EPM5192AJM84-15 vs EPM5192ALC84-15 Vergleich
Detaillierter Direktvergleich von EPM5192AJM84-15 von Altera und EPM5192ALC84-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192AJM84-15 | EPM5192ALC84-15 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $21,00 | $13,20 |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | CPLD / UV-Erasable / OTP Complex PLD |
| Family | MAX 5000 | — |
| Macrocells | 192 | 192 |
| User I/O Pins | 84 | 64 |
| Speed Grade | -15 (15 ns tPD) | — |
| Propagation Delay (tPD) | 15 ns | 15 ns |
| Maximum Operating Frequency | 83.3 MHz | — |
| Process Technology | 5 V CMOS, UV-EPROM | CMOS (EPROM-based) |
| Gehäuse | 84-pin ceramic J-lead (JM84) | 84-pin PLCC (QCCJ, J-bend ceramic) |
| Montageart | Surface Mount (ceramic J-lead) | — |
| Betriebstemperaturbereich | -55C to +125C (military grade) | — |
| Versorgungsspannung | [DATA_NEEDED: VCC range] | — |
| Erase Method | Ultraviolet (windowed ceramic package) | — |
| Programming Method | EPROM-style (programmer + UV erase) | — |
| I/O Standard | TTL-compatible CMOS | — |
| Development Tool | Altera MAX+PLUS II | — |
| RoHS-Status | Non-compliant (ceramic with UV window) | — |
| Lebenszyklusstatus | Obsolete (EOL by Altera, now supported by Microchip / 3rd-party distributors) | — |
| Device Family | — | MAX 5000 (EPM5192) |
| Dedicated Inputs | — | 7 |
| Propagation Delay (Industry Variant) | — | 25 ns (per MicrochipUSA listing) |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (nominal 5 V) |
| Programmability | — | UV-erasable window / OTP |
| Operating Temperature Grade | — | Commercial |
| Terminal Form | — | J-BEND |
| Package Code | — | QCCJ |
| Package Shape | — | SQUARE |
| Architecture | — | Programmable Logic Array + Macrocell Registers + PIA interconnect |