EPM5192AQC100-15 vs EPM5192AGC84-20 Vergleich
Detaillierter Direktvergleich von EPM5192AQC100-15 von Altera und EPM5192AGC84-20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192AQC100-15 | EPM5192AGC84-20 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,95 | $41,20 |
| Manufacturer | Altera (now Intel) | — |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-Erasable / OTP Complex PLD (CPLD) | — |
| Technology | CMOS | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| Propagation Delay (tPD) | 25 ns (-15 speed grade) | — |
| Total Inputs | 72 | — |
| Dedicated Inputs | 7 | 7 |
| User I/O Pins | 64 | 64 |
| External Clock Inputs | 1 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Gehäuse | 100-pin PQFP (R-PQFP-G100) | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) |
| Montageart | Surface Mount | Through-Hole (Pin Grid Array socket) |
| Configuration Memory | EPROM (UV-erasable, OTP) | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance] |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | — |
| Product Type | — | Complex Programmable Logic Device (CPLD) |
| Logic Gates (typical) | — | [DATA_NEEDED: typical gate count] |
| Maximum Clock Frequency (fMAX) | — | 66.7 MHz |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Speed Grade | — | -20 |
| Package Code | — | WPGA |
| Erasure Method | — | UV-Erasable (with OTP window) |
| Process Technology | — | CMOS |
| Operating Temperature Grade | — | Commercial |
| Versorgungsspannung | — | [DATA_NEEDED: VCC range] |
| I/O Standard | — | 5V CMOS / TTL compatible |