EPM5192AQC100-15 vs EPM5192AGC84-20 Comparación
Comparación detallada lado a lado de EPM5192AQC100-15 por Altera y EPM5192AGC84-20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192AQC100-15 | EPM5192AGC84-20 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,95 | $41,20 |
| Manufacturer | Altera (now Intel) | — |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-Erasable / OTP Complex PLD (CPLD) | — |
| Technology | CMOS | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| Propagation Delay (tPD) | 25 ns (-15 speed grade) | — |
| Total Inputs | 72 | — |
| Dedicated Inputs | 7 | 7 |
| User I/O Pins | 64 | 64 |
| External Clock Inputs | 1 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Encapsulado | 100-pin PQFP (R-PQFP-G100) | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) |
| Tipo de montaje | Surface Mount | Through-Hole (Pin Grid Array socket) |
| Configuration Memory | EPROM (UV-erasable, OTP) | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance] |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | — |
| Product Type | — | Complex Programmable Logic Device (CPLD) |
| Logic Gates (typical) | — | [DATA_NEEDED: typical gate count] |
| Maximum Clock Frequency (fMAX) | — | 66.7 MHz |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Speed Grade | — | -20 |
| Package Code | — | WPGA |
| Erasure Method | — | UV-Erasable (with OTP window) |
| Process Technology | — | CMOS |
| Operating Temperature Grade | — | Commercial |
| Tensión de alimentación | — | [DATA_NEEDED: VCC range] |
| I/O Standard | — | 5V CMOS / TTL compatible |