EPM5192JC-1 vs EPM5192JC Vergleich

Detaillierter Direktvergleich von EPM5192JC-1 von Altera und EPM5192JC von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5192JC-1 EPM5192JC
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $22,40 $16,40
Family MAX 5000 —
Device Type CPLD - Complex Programmable Logic Device —
Technology CMOS, UV-Erasable / OTP —
Macrocells 192 192
Usable Gates 3750 —
Propagation Delay (tPD) 40 ns (speed grade -1) —
Maximum Internal Frequency (fMAX) 62.5 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V —
User I/O Pins 84 —
Package Type 84-pin Ceramic Quad Flat Pack (CQFP), windowed —
JEDEC Package Code S-CQCC-J84 —
Betriebstemperatur 0 C to +70 C (commercial) [DATA_NEEDED: commercial / industrial / military grade]
Configuration Memory UV-EPROM (erasable under UV lamp) —
Programming Interface Altera MAX programming interface (parallel, pre-JTAG for this family) —
Process CMOS EPROM —
I/O Standard TTL/CMOS 5 V compatible —
Product Type — CPLD (Complex Programmable Logic Device)
Series — EPM5192 (Classic / MAX-class)
Logic Array Blocks (LABs) — 12
Interconnect Architecture — Programmable Interconnect Array (PIA)
Process Technology — CMOS EPROM (UV-erasable)
Gehäuse — 68-pin PLCC (JC) windowed ceramic
Montageart — Surface Mount
Programming Method — UV-erase + EPROM programmer
Non-Volatile Configuration — Yes (EPROM cell array)
Logic Family — Classic CPLD (EPM5xxx series)
Versorgungsspannung — [DATA_NEEDED: VCC nominal]
Propagation Delay — [DATA_NEEDED: tpd spec by speed grade]
RoHS-Status — [DATA_NEEDED: original Altera marking not RoHS]

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