EPM5192JC-1 vs EPM5192JC 비교
다음의 상세 나란히 비교: EPM5192JC-1 제조: Altera 및 EPM5192JC 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5192JC-1 | EPM5192JC |
|---|---|---|
| 브랜드 | Altera | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $22.40 | $16.40 |
| Family | MAX 5000 | — |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Technology | CMOS, UV-Erasable / OTP | — |
| Macrocells | 192 | 192 |
| Usable Gates | 3750 | — |
| Propagation Delay (tPD) | 40 ns (speed grade -1) | — |
| Maximum Internal Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| User I/O Pins | 84 | — |
| Package Type | 84-pin Ceramic Quad Flat Pack (CQFP), windowed | — |
| JEDEC Package Code | S-CQCC-J84 | — |
| 동작 온도 | 0 C to +70 C (commercial) | [DATA_NEEDED: commercial / industrial / military grade] |
| Configuration Memory | UV-EPROM (erasable under UV lamp) | — |
| Programming Interface | Altera MAX programming interface (parallel, pre-JTAG for this family) | — |
| Process | CMOS EPROM | — |
| I/O Standard | TTL/CMOS 5 V compatible | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Series | — | EPM5192 (Classic / MAX-class) |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect Architecture | — | Programmable Interconnect Array (PIA) |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| 패키지 | — | 68-pin PLCC (JC) windowed ceramic |
| 실장 유형 | — | Surface Mount |
| Programming Method | — | UV-erase + EPROM programmer |
| Non-Volatile Configuration | — | Yes (EPROM cell array) |
| Logic Family | — | Classic CPLD (EPM5xxx series) |
| 공급 전압 | — | [DATA_NEEDED: VCC nominal] |
| Propagation Delay | — | [DATA_NEEDED: tpd spec by speed grade] |
| RoHS 상태 | — | [DATA_NEEDED: original Altera marking not RoHS] |