EPM5192JC-2 vs EPM5192GM883B-2 Vergleich
Detaillierter Direktvergleich von EPM5192JC-2 von Altera und EPM5192GM883B-2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192JC-2 | EPM5192GM883B-2 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $22,50 | $142,00 |
| Device Family | MAX 5000 | — |
| Product Type | UV-erasable Programmable Logic Device (PLD) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| User I/O Pins | 64 | 64 |
| Dedicated Inputs | 7 | 7 |
| External Clock Inputs | 1 | — |
| Propagation Delay (tPD) | 45 ns | 45 ns (-2 speed grade) |
| Maximale Taktfrequenz | 40 MHz | — |
| Process Technology | CMOS | — |
| Gehäuse | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) | 84-pin Ceramic Pin Grid Array (CPGA), code S-CPGA-P84 |
| Montageart | Surface Mount | Through-hole PGA socket |
| Number of Terminals | 84 | — |
| Programming Method | UV-erase / EPROM | — |
| Betriebstemperaturbereich | [DATA_NEEDED: operating temperature range] | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | non_compliant (ceramic CPGA with MIL-STD-883 screening) |
| Family | — | MAX 5000 |
| Device Type | — | CPLD (Complex Programmable Logic Device), UV-erasable |
| Maximum Internal Clock Frequency | — | 33.3 MHz |
| Supply Voltage (VCC, nominal) | — | 5 V |
| Technology | — | 5 V CMOS |
| Package Outline | — | 28.45 mm square (approx.) |
| Military Screening | — | MIL-STD-883 (per '883' suffix) |
| Betriebstemperatur | — | [DATA_NEEDED: operating temperature range] |
| JEDEC Package Code | — | S-CPGA-P84 |