EPM5192JC2 vs EPM5192JC-ES Vergleich
Detaillierter Direktvergleich von EPM5192JC2 von Intel und EPM5192JC-ES von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192JC2 | EPM5192JC-ES |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $15,90 | $16,45 |
| Family | MAX 5000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (EPLD) |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Usable Gates (equivalent) | 6000 | — |
| Maximum User I/O | 64 | — |
| Dedicated Inputs | 7 | — |
| External Clock Inputs | 1 (with shared input/clock capability) | — |
| Maximale Taktfrequenz | 50 MHz | — |
| Propagation Delay (tPD) | 45 ns (speed grade -2) | — |
| Process Technology | CMOS, UV-erasable | — |
| Interconnect | Programmable Interconnect Array (PIA) | Programmable Interconnect Array (PIA) |
| Gehäuse | PLCC-68 (JC) | 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) |
| Montageart | Surface Mount (socketable PLCC) | Surface Mount |
| Programming | Altera Master Programmer / ByteBlaster via JTAG-style interface | Altera MAX+PLUS II or compatible programmer |
| Device Family | — | MAX 5000 |
| Configuration Memory | — | EPROM (UV-erasable, one-time programmable for JC-ES) |
| Technology | — | CMOS |
| Betriebstemperatur | — | [DATA_NEEDED: operating temperature range for ES grade] |
| Versorgungsspannung | — | [DATA_NEEDED: VCC nominal] |
| User I/O Pins | — | [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] |
| RoHS-Status | — | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| MSL-Level | — | [DATA_NEEDED: MSL rating] |
| Note | — | Datasheet source: Altera MAX 5000 family document, 52 pages |