EPM5192JI-2 vs EPM5192JC-2 Vergleich
Detaillierter Direktvergleich von EPM5192JI-2 von Altera und EPM5192JC-2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192JI-2 | EPM5192JC-2 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,95 | $22,50 |
| Family | MAX 5000 | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Usable Gates | 5000 | — |
| Dedicated Inputs | 12 | 7 |
| Flip-Flops | 192 | — |
| Speed Grade | -2 | — |
| Gehäuse | JLCC-68 (J-Lead Ceramic) | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) |
| Betriebstemperatur | 0C to +70C (commercial) | — |
| Programming Technology | UV-Erasable EPROM | — |
| Architecture | Sum-of-products with Programmable Interconnect Array (PIA) | — |
| Versorgungsspannung | 5 V (typical) | — |
| Process Technology | CMOS EPROM | CMOS |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | Non-compliant (ceramic JLCC, contains lead) | [DATA_NEEDED: RoHS compliance] |
| Lebenszyklusstatus | Obsolete (legacy Altera MAX 5000 family) | — |
| Device Family | — | MAX 5000 |
| Product Type | — | UV-erasable Programmable Logic Device (PLD) |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| User I/O Pins | — | 64 |
| External Clock Inputs | — | 1 |
| Propagation Delay (tPD) | — | 45 ns |
| Maximale Taktfrequenz | — | 40 MHz |
| Number of Terminals | — | 84 |
| Programming Method | — | UV-erase / EPROM |
| Betriebstemperaturbereich | — | [DATA_NEEDED: operating temperature range] |