EPM5192JI-2 vs EPM5192JC-2 Comparison
Detailed side-by-side comparison of EPM5192JI-2 by Altera and EPM5192JC-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192JI-2 | EPM5192JC-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Usable Gates | 5000 | — |
| Dedicated Inputs | 12 | 7 |
| Flip-Flops | 192 | — |
| Speed Grade | -2 | — |
| Package | JLCC-68 (J-Lead Ceramic) | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) |
| Operating Temperature | 0C to +70C (commercial) | — |
| Programming Technology | UV-Erasable EPROM | — |
| Architecture | Sum-of-products with Programmable Interconnect Array (PIA) | — |
| Supply Voltage | 5 V (typical) | — |
| Process Technology | CMOS EPROM | CMOS |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Non-compliant (ceramic JLCC, contains lead) | [DATA_NEEDED: RoHS compliance] |
| Lifecycle Status | Obsolete (legacy Altera MAX 5000 family) | — |
| Device Family | — | MAX 5000 |
| Product Type | — | UV-erasable Programmable Logic Device (PLD) |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| User I/O Pins | — | 64 |
| External Clock Inputs | — | 1 |
| Propagation Delay (tPD) | — | 45 ns |
| Maximum Clock Frequency | — | 40 MHz |
| Number of Terminals | — | 84 |
| Programming Method | — | UV-erase / EPROM |
| Operating Temperature Range | — | [DATA_NEEDED: operating temperature range] |