EPM5192LC-2 vs EPM5192LC Vergleich
Detaillierter Direktvergleich von EPM5192LC-2 von Altera und EPM5192LC von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192LC-2 | EPM5192LC |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,95 | $28,40 |
| Family | MAX 5000 | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| User I/O Pins | 64 | 64 |
| Dedicated Input Pins | 7 | — |
| External Clock Inputs | 1 | — |
| Propagation Delay (tPD) | 45 ns (typical, -2 speed grade) | 55 ns (typical, commercial) |
| Maximum Internal Frequency | 50 MHz | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Process Technology | CMOS | CMOS, UV-erasable/OTP EPROM configuration |
| Gehäuse | PQCC-84 (PLCC-84, J-lead, surface mount) | JLCC-68 (windowed ceramic, LC suffix) |
| Programming | Non-volatile (EPROM/EEPROM-based, in-system programmable via JTAG) | — |
| Betriebstemperatur | [DATA_NEEDED: commercial/industrial/military grade] | — |
| Versorgungsspannung | 5 V (typical MAX 5000 family) | — |
| RoHS-Status | [DATA_NEEDED: pre-RoHS legacy part — likely non-RoHS] | [DATA_NEEDED: RoHS status] |
| Dedicated Inputs | — | 7 |
| Global Clock Inputs | — | 1 |
| Maximum Clock Frequency (fMAX) | — | 50 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (nominal 5 V) |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA), fixed delay |
| Boundary-Scan Support | — | JTAG IEEE 1149.1 |
| Programming Interface | — | JTAG (ByteBlaster-compatible) |
| Operating Temperature (commercial) | — | 0C to +70C |
| Montageart | — | Surface Mount |