EPM5192LC-25 vs EPM5192LC-M091A Vergleich

Detaillierter Direktvergleich von EPM5192LC-25 von Altera und EPM5192LC-M091A von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5192LC-25 EPM5192LC-M091A
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $55,00 $62,00
Product Type CPLD (Complex Programmable Logic Device) —
Family MAX 5000 —
Macrocells 192 192
Logic Elements 192 (1 macrocell ≈ 1 LE in MAX 5000 architecture) —
Pin-to-Pin Delay (tPD) 25 ns —
Speed Grade -25 (25 ns) —
Gehäuse JLCC-84 (ceramic J-lead chip carrier) LC (custom pin-grid / customer-specific, M091A designation)
Montageart Surface Mount —
Programmable Technology UV-erasable / OTP (EPROM-based) —
Programming Interface JTAG / Altera programming hardware (legacy) —
Betriebstemperatur 0C to +70C (commercial) [DATA_NEEDED: operating temperature grade]
Versorgungsspannung 5 V (typical, MAX 5000) —
I/O Standard TTL-compatible —
Configuration Memory Non-volatile EPROM (on-chip) Non-volatile EPROM (UV-erasable)
Manufacturer Altera Corporation (now Intel PSG) —
RoHS-Status Unknown (legacy ceramic package typically non-RoHS) [DATA_NEEDED: RoHS status for EPM5192LC-M091A]
Device Family — MAX 5000 EPLD
User I/O Pins — 64
Dedicated Inputs — 7
Logic Array Blocks (LABs) — 12
Global Clock Inputs — 1
Propagation Delay (tpd) — 55 ns (typical, MAX 5000 family)
Supply Voltage (Vcc) — 5 V
Technology — UV-erasable CMOS, EPROM-based
Interconnect — Programmable Interconnect Array (PIA)
Pin-Anzahl — [DATA_NEEDED: pin count of LC-M091A package]
Development Tool — Altera MAX+PLUS II (legacy)

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