EPM5192LC-25 vs EPM5192LC-M091A 对比

详细并排对比 EPM5192LC-25 出自 Altera 和 EPM5192LC-M091A 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5192LC-25 EPM5192LC-M091A
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $55.00 $62.00
Product Type CPLD (Complex Programmable Logic Device) —
Family MAX 5000 —
Macrocells 192 192
Logic Elements 192 (1 macrocell ≈ 1 LE in MAX 5000 architecture) —
Pin-to-Pin Delay (tPD) 25 ns —
Speed Grade -25 (25 ns) —
封装 JLCC-84 (ceramic J-lead chip carrier) LC (custom pin-grid / customer-specific, M091A designation)
安装类型 Surface Mount —
Programmable Technology UV-erasable / OTP (EPROM-based) —
Programming Interface JTAG / Altera programming hardware (legacy) —
工作温度 0C to +70C (commercial) [DATA_NEEDED: operating temperature grade]
电源电压 5 V (typical, MAX 5000) —
I/O Standard TTL-compatible —
Configuration Memory Non-volatile EPROM (on-chip) Non-volatile EPROM (UV-erasable)
Manufacturer Altera Corporation (now Intel PSG) —
RoHS 状态 Unknown (legacy ceramic package typically non-RoHS) [DATA_NEEDED: RoHS status for EPM5192LC-M091A]
Device Family — MAX 5000 EPLD
User I/O Pins — 64
Dedicated Inputs — 7
Logic Array Blocks (LABs) — 12
Global Clock Inputs — 1
Propagation Delay (tpd) — 55 ns (typical, MAX 5000 family)
Supply Voltage (Vcc) — 5 V
Technology — UV-erasable CMOS, EPROM-based
Interconnect — Programmable Interconnect Array (PIA)
引脚数量 — [DATA_NEEDED: pin count of LC-M091A package]
Development Tool — Altera MAX+PLUS II (legacy)

数据手册与资源

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