EPM5192LC-2N vs EPM5192LC-35 Vergleich

Detaillierter Direktvergleich von EPM5192LC-2N von Altera und EPM5192LC-35 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5192LC-2N EPM5192LC-35
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $11,85 $15,25
Family MAX 5000 MAX 5000 CPLD
Macrocells 192 —
Flip-Flops 192 —
Logic Elements 192 macrocells (PAL/GAL-style AND-OR array) —
Package Type LC (ceramic J-leaded, windowed UV-erasable package family) JLCC (J-Lead Ceramic Chip Carrier)
Speed Grade -2 (tPD approximately 25 ns) -35
Propagation Delay (typical) 25 ns —
Versorgungsspannung 5 V (typical) —
Programmability UV-erasable EPROM cell —
Montageart Surface Mount (LC package) Surface Mount
Betriebstemperatur Commercial (0C to +70C) - inferred from speed-grade -2 designation Commercial (0C to +70C) per LC suffix
RoHS-Status Compliant (per -N lead-free suffix) Non-compliant (ceramic hermetic package)
Lead-Free Yes (per -N suffix) —
Architecture Programmable Logic Array (PLA) with global PIA LAB-based with Programmable Interconnect Array (PIA)
Programming Interface Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) —
Series — MAX 5000
Logic Elements / Macrocells — 192 macrocells
Pin-to-Pin Delay (tPD) — 35 ns
Programmable Type — UV-Erasable / OTP (EPROM-based)
Logic Voltage — 5 V TTL-compatible I/O
Programming Method — Altera legacy programmer (EPROM-based)
I/O Standard — TTL
Lebenszyklusstatus — Obsolete - last-time-buy stock only
Datasheet Document — Altera MAX 5000 family datasheet (per alldatasheet.com)

Datenblätter & Ressourcen

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