EPM5192LC-2N vs EPM5192LC-35 Comparison
Detailed side-by-side comparison of EPM5192LC-2N by Altera and EPM5192LC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192LC-2N | EPM5192LC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 CPLD |
| Macrocells | 192 | — |
| Flip-Flops | 192 | — |
| Logic Elements | 192 macrocells (PAL/GAL-style AND-OR array) | — |
| Package Type | LC (ceramic J-leaded, windowed UV-erasable package family) | JLCC (J-Lead Ceramic Chip Carrier) |
| Speed Grade | -2 (tPD approximately 25 ns) | -35 |
| Propagation Delay (typical) | 25 ns | — |
| Supply Voltage | 5 V (typical) | — |
| Programmability | UV-erasable EPROM cell | — |
| Mounting Type | Surface Mount (LC package) | Surface Mount |
| Operating Temperature | Commercial (0C to +70C) - inferred from speed-grade -2 designation | Commercial (0C to +70C) per LC suffix |
| RoHS Status | Compliant (per -N lead-free suffix) | Non-compliant (ceramic hermetic package) |
| Lead-Free | Yes (per -N suffix) | — |
| Architecture | Programmable Logic Array (PLA) with global PIA | LAB-based with Programmable Interconnect Array (PIA) |
| Programming Interface | Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) | — |
| Series | — | MAX 5000 |
| Logic Elements / Macrocells | — | 192 macrocells |
| Pin-to-Pin Delay (tPD) | — | 35 ns |
| Programmable Type | — | UV-Erasable / OTP (EPROM-based) |
| Logic Voltage | — | 5 V TTL-compatible I/O |
| Programming Method | — | Altera legacy programmer (EPROM-based) |
| I/O Standard | — | TTL |
| Lifecycle Status | — | Obsolete - last-time-buy stock only |
| Datasheet Document | — | Altera MAX 5000 family datasheet (per alldatasheet.com) |