EPM5192LC-35 vs EPM5192LC-M091A Vergleich

Detaillierter Direktvergleich von EPM5192LC-35 von Altera und EPM5192LC-M091A von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5192LC-35 EPM5192LC-M091A
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $15,25 $62,00
Series MAX 5000 —
Family MAX 5000 CPLD —
Logic Elements / Macrocells 192 macrocells —
Pin-to-Pin Delay (tPD) 35 ns —
Speed Grade -35 —
Programmable Type UV-Erasable / OTP (EPROM-based) —
Package Type JLCC (J-Lead Ceramic Chip Carrier) —
Montageart Surface Mount —
Logic Voltage 5 V TTL-compatible I/O —
Betriebstemperatur Commercial (0C to +70C) per LC suffix [DATA_NEEDED: operating temperature grade]
Programming Method Altera legacy programmer (EPROM-based) —
Architecture LAB-based with Programmable Interconnect Array (PIA) —
I/O Standard TTL —
RoHS-Status Non-compliant (ceramic hermetic package) [DATA_NEEDED: RoHS status for EPM5192LC-M091A]
Lebenszyklusstatus Obsolete - last-time-buy stock only —
Datasheet Document Altera MAX 5000 family datasheet (per alldatasheet.com) —
Device Family — MAX 5000 EPLD
Macrocells — 192
User I/O Pins — 64
Dedicated Inputs — 7
Logic Array Blocks (LABs) — 12
Global Clock Inputs — 1
Propagation Delay (tpd) — 55 ns (typical, MAX 5000 family)
Supply Voltage (Vcc) — 5 V
Technology — UV-erasable CMOS, EPROM-based
Interconnect — Programmable Interconnect Array (PIA)
Gehäuse — LC (custom pin-grid / customer-specific, M091A designation)
Pin-Anzahl — [DATA_NEEDED: pin count of LC-M091A package]
Configuration Memory — Non-volatile EPROM (UV-erasable)
Development Tool — Altera MAX+PLUS II (legacy)

Datenblätter & Ressourcen

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