EPM5192LC84-2 vs EPM5192LC-1 Vergleich
Detaillierter Direktvergleich von EPM5192LC84-2 von Altera und EPM5192LC-1 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192LC84-2 | EPM5192LC-1 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,10 | $14,20 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (UV-Erasable / OTP Complex PLD) | EPLD / CPLD |
| Macrocells | 192 | 192 |
| Gehäuse | 84-pin PLCC (LC) | — |
| Speed Grade | -2 | -1 |
| Versorgungsspannung | 5 V (TTL-compatible I/O) | 5 V nominal (4.75 V to 5.25 V) |
| Technology | CMOS, UV-erasable / OTP | CMOS, UV-erasable / OTP EPROM cell |
| Logic Elements | AND-OR array with macrocell flip-flops | — |
| Programming Method | Altera legacy programmer (JEDEC bitstream) | — |
| Betriebstemperatur | Commercial (0C to +70C) | 0C to +70C (commercial) |
| Montageart | Surface Mount | — |
| RoHS-Status | Non-compliant (SnPb lead finish typical for this vintage) | Non-compliant (ceramic LDCC with Pb-bearing terminations) |
| Lebenszyklusstatus | Obsolete (last Altera MAX 5000 production) | — |
| JTAG Support | Vendor-specific programming interface (pre-IEEE 1532) | — |
| I/O Standard | TTL, 5V CMOS-compatible | — |
| Logic Gates | — | 3750 (typical usable) |
| Dedicated Inputs | — | 7 |
| User I/O | — | 64 |
| Anzahl der Pins | — | 84 |
| Package Type | — | LDCC (Leaded Ceramic Chip Carrier), plastic windowless |
| Propagation Delay | — | 25 ns |
| Maximale Taktfrequenz | — | 50 MHz |
| Programmable Memory | — | EPROM (one-time or UV-erasable) |