EPM5192LC84-2 vs EPM5192LC84 Vergleich
Detaillierter Direktvergleich von EPM5192LC84-2 von Altera und EPM5192LC84 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192LC84-2 | EPM5192LC84 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,10 | $15,95 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (UV-Erasable / OTP Complex PLD) | — |
| Macrocells | 192 | — |
| Gehäuse | 84-pin PLCC (LC) | LCC-84 (PQCC84, MS-018) |
| Speed Grade | -2 | — |
| Versorgungsspannung | 5 V (TTL-compatible I/O) | [DATA_NEEDED: VCC range] |
| Technology | CMOS, UV-erasable / OTP | — |
| Logic Elements | AND-OR array with macrocell flip-flops | — |
| Programming Method | Altera legacy programmer (JEDEC bitstream) | — |
| Betriebstemperatur | Commercial (0C to +70C) | [DATA_NEEDED: operating temperature range] |
| Montageart | Surface Mount | Surface Mount (Socket-compatible) |
| RoHS-Status | Non-compliant (SnPb lead finish typical for this vintage) | unknown |
| Lebenszyklusstatus | Obsolete (last Altera MAX 5000 production) | — |
| JTAG Support | Vendor-specific programming interface (pre-IEEE 1532) | — |
| I/O Standard | TTL, 5V CMOS-compatible | — |
| Product Type | — | Complex Programmable Logic Device (CPLD) |
| Macrocells (Logic Cells) | — | 192 |
| Propagation Delay (tPD) | — | 55 ns |
| Process Technology | — | CMOS |
| Programmability | — | OTP / UV-Erasable |
| Pin-Anzahl | — | 84 |
| User I/O | — | [DATA_NEEDED: max user I/O count] |
| Configuration Memory | — | EPROM / UV-Erasable |
| Programming Interface | — | JTAG / Altera legacy (MAX+PLUS II baseline) |
| MSL-Level | — | [DATA_NEEDED: MSL rating] |