EPM5192LC84-2 vs EPM5192LC84 Comparación
Comparación detallada lado a lado de EPM5192LC84-2 por Altera y EPM5192LC84 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192LC84-2 | EPM5192LC84 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $7,10 | $15,95 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (UV-Erasable / OTP Complex PLD) | — |
| Macrocells | 192 | — |
| Encapsulado | 84-pin PLCC (LC) | LCC-84 (PQCC84, MS-018) |
| Speed Grade | -2 | — |
| Tensión de alimentación | 5 V (TTL-compatible I/O) | [DATA_NEEDED: VCC range] |
| Technology | CMOS, UV-erasable / OTP | — |
| Logic Elements | AND-OR array with macrocell flip-flops | — |
| Programming Method | Altera legacy programmer (JEDEC bitstream) | — |
| Temperatura de funcionamiento | Commercial (0C to +70C) | [DATA_NEEDED: operating temperature range] |
| Tipo de montaje | Surface Mount | Surface Mount (Socket-compatible) |
| Estado RoHS | Non-compliant (SnPb lead finish typical for this vintage) | unknown |
| Estado del ciclo de vida | Obsolete (last Altera MAX 5000 production) | — |
| JTAG Support | Vendor-specific programming interface (pre-IEEE 1532) | — |
| I/O Standard | TTL, 5V CMOS-compatible | — |
| Product Type | — | Complex Programmable Logic Device (CPLD) |
| Macrocells (Logic Cells) | — | 192 |
| Propagation Delay (tPD) | — | 55 ns |
| Process Technology | — | CMOS |
| Programmability | — | OTP / UV-Erasable |
| Recuento de pines | — | 84 |
| User I/O | — | [DATA_NEEDED: max user I/O count] |
| Configuration Memory | — | EPROM / UV-Erasable |
| Programming Interface | — | JTAG / Altera legacy (MAX+PLUS II baseline) |
| Nivel MSL | — | [DATA_NEEDED: MSL rating] |