EPM5192LI-1 vs EPM5192IC-1 Vergleich

Detaillierter Direktvergleich von EPM5192LI-1 von Altera und EPM5192IC-1 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5192LI-1 EPM5192IC-1
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $16,40 $13,95
Family MAX 5000 MAX 5000 EPLD
Device Type EPLD (UV-Erasable/OTP Complex PLD) —
Usable Gates 3,750 3750
Macrocells 192 192
Maximum Toggle Frequency 40 MHz —
Versorgungsspannung 5 V —
Propagation Delay (tPD) [DATA_NEEDED: tPD in ns at -1 grade] —
User I/O Pins [DATA_NEEDED: user I/O count for JLCC variant] —
Package Type JLCC (windowed, ceramic, UV-erasable) —
Process Technology CMOS EPROM, UV-erasable —
Speed Grade -1 —
Betriebstemperatur [DATA_NEEDED: industrial vs military range] -40C to +85C (industrial)
Pin-Anzahl [DATA_NEEDED: pin count of LI package] —
Montageart Surface Mount (JLCC with J-leads) —
MSL-Level [DATA_NEEDED: MSL level] —
RoHS-Status [DATA_NEEDED: RoHS status of ceramic LI variant] —
Lead Free [DATA_NEEDED: lead-free] —
Programmable Interconnect Programmable Interconnect Array (PIA) —
Architecture EEPROM/EPROM-based, non-volatile, instant-on —
Dedicated Inputs — 7
I/O Pins — 64
Pin-to-Pin Delay (tPD) — 15 ns (max, -1 speed grade)
Counter Frequency (fCNT) — 76.9 MHz
Supply Voltage (VCC) — 4.75 V to 5.25 V (nominal 5 V)
Technology — CMOS, UV-erasable, in-system programmable
Gehäuse — 68-pin ceramic J-lead (IC-1 suffix)
Programming Interface — JTAG / IEEE Std 1149.1 boundary scan
Security Bit — Yes (design protection)
Supply Current (Icc, typical) — [DATA_NEEDED: Icc] mA
Output Drive Current (IOH/IOL) — [DATA_NEEDED: IOH/IOL] mA

Datenblätter & Ressourcen

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