EPM5192LI-1 vs EPM5192IC-1 Comparación
Comparación detallada lado a lado de EPM5192LI-1 por Altera y EPM5192IC-1 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192LI-1 | EPM5192IC-1 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $16,40 | $13,95 |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device Type | EPLD (UV-Erasable/OTP Complex PLD) | — |
| Usable Gates | 3,750 | 3750 |
| Macrocells | 192 | 192 |
| Maximum Toggle Frequency | 40 MHz | — |
| Tensión de alimentación | 5 V | — |
| Propagation Delay (tPD) | [DATA_NEEDED: tPD in ns at -1 grade] | — |
| User I/O Pins | [DATA_NEEDED: user I/O count for JLCC variant] | — |
| Package Type | JLCC (windowed, ceramic, UV-erasable) | — |
| Process Technology | CMOS EPROM, UV-erasable | — |
| Speed Grade | -1 | — |
| Temperatura de funcionamiento | [DATA_NEEDED: industrial vs military range] | -40C to +85C (industrial) |
| Recuento de pines | [DATA_NEEDED: pin count of LI package] | — |
| Tipo de montaje | Surface Mount (JLCC with J-leads) | — |
| Nivel MSL | [DATA_NEEDED: MSL level] | — |
| Estado RoHS | [DATA_NEEDED: RoHS status of ceramic LI variant] | — |
| Lead Free | [DATA_NEEDED: lead-free] | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| Architecture | EEPROM/EPROM-based, non-volatile, instant-on | — |
| Dedicated Inputs | — | 7 |
| I/O Pins | — | 64 |
| Pin-to-Pin Delay (tPD) | — | 15 ns (max, -1 speed grade) |
| Counter Frequency (fCNT) | — | 76.9 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (nominal 5 V) |
| Technology | — | CMOS, UV-erasable, in-system programmable |
| Encapsulado | — | 68-pin ceramic J-lead (IC-1 suffix) |
| Programming Interface | — | JTAG / IEEE Std 1149.1 boundary scan |
| Security Bit | — | Yes (design protection) |
| Supply Current (Icc, typical) | — | [DATA_NEEDED: Icc] mA |
| Output Drive Current (IOH/IOL) | — | [DATA_NEEDED: IOH/IOL] mA |