EPM7128STC100-10 vs EPM7128SQC100-15 Vergleich
Detaillierter Direktvergleich von EPM7128STC100-10 von Altera und EPM7128SQC100-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM7128STC100-10 - 128-Macro MAX 7000S CPLD, 10ns TQFP-100 | Intel / Altera
EPM7128STC100-10 ObsoleteAltera
EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel
EPM7128SQC100-15 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM7128STC100-10 | EPM7128SQC100-15 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,10 | $8,20 |
| Family | MAX 7000S | MAX 7000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 | — |
| Usable Gates | 2,500 | — |
| User I/Os | 84 | 84 |
| Logic Array Blocks | 8 (16 macrocells per LAB) | — |
| Propagation Delay (tPD) | 10 ns | — |
| Internal Counter Frequency (fCNT) | 100 MHz | — |
| Logic Family | CMOS | — |
| Supply Voltage (VCCINT) | 5 V | 5 V (5% tolerance) |
| MultiVolt I/O Voltage | 3.3 V / 5 V | — |
| Gehäuse | TQFP-100 (C100) | 100-pin PQFP (Plastic Quad Flat Pack) |
| Pin-Anzahl | 100 | — |
| Montageart | Surface Mount | Surface Mount |
| Programmability | In-System Programmable (JTAG, IEEE 1149.1), EEPROM | — |
| Betriebstemperatur | 0C to +70C (commercial) | 0C to +70C (Commercial) |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status not in provided data] | Non-compliant (SnPb lead finish - legacy PQFP) |
| Macrocells | — | 128 |
| Logic Array Blocks (LABs) | — | 4 (16 macrocells each) |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fMAX value] |
| Typical Gate Count | — | 2,500 gates |
| Programming Technology | — | EEPROM (in-system programmable via JTAG) |
| JTAG Interface | — | IEEE Std. 1149.1 compliant |
| MSL-Level | — | 3 (168 hours) |