EPM7128STC100-10 vs EPM7128SQC100-15 Comparison

Detailed side-by-side comparison of EPM7128STC100-10 by Altera and EPM7128SQC100-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM7128SQC100-15 EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel

EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel

EPM7128SQC100-15 ⚠ Last Time Buy

Specification Comparison

Parameter EPM7128STC100-10 EPM7128SQC100-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Last Time Buy
Unit Price (USD) — $8.20
Family MAX 7000S MAX 7000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macro Cells 128 —
Usable Gates 2,500 —
User I/Os 84 84
Logic Array Blocks 8 (16 macrocells per LAB) —
Propagation Delay (tPD) 10 ns —
Internal Counter Frequency (fCNT) 100 MHz —
Logic Family CMOS —
Supply Voltage (VCCINT) 5 V 5 V (5% tolerance)
MultiVolt I/O Voltage 3.3 V / 5 V —
Package TQFP-100 (C100) 100-pin PQFP (Plastic Quad Flat Pack)
Pin Count 100 —
Mounting Type Surface Mount Surface Mount
Programmability In-System Programmable (JTAG, IEEE 1149.1), EEPROM —
Operating Temperature 0C to +70C (commercial) 0C to +70C (Commercial)
RoHS Status [DATA_NEEDED: RoHS compliance status not in provided data] Non-compliant (SnPb lead finish - legacy PQFP)
Macrocells — 128
Logic Array Blocks (LABs) — 4 (16 macrocells each)
Pin-to-Pin Delay (tPD) — 15 ns
Maximum Frequency (fMAX) — [DATA_NEEDED: fMAX value]
Typical Gate Count — 2,500 gates
Programming Technology — EEPROM (in-system programmable via JTAG)
JTAG Interface — IEEE Std. 1149.1 compliant
MSL Level — 3 (168 hours)

Datasheets & Resources

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