EPM7128STC100-10 vs EPM7128SQC100-15 对比
详细并排对比 EPM7128STC100-10 出自 Altera 和 EPM7128SQC100-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPM7128STC100-10 - 128-Macro MAX 7000S CPLD, 10ns TQFP-100 | Intel / Altera
EPM7128STC100-10 Obsolete
规格对比
| 参数 | EPM7128STC100-10 | EPM7128SQC100-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $7.10 | $8.20 |
| Family | MAX 7000S | MAX 7000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 | — |
| Usable Gates | 2,500 | — |
| User I/Os | 84 | 84 |
| Logic Array Blocks | 8 (16 macrocells per LAB) | — |
| Propagation Delay (tPD) | 10 ns | — |
| Internal Counter Frequency (fCNT) | 100 MHz | — |
| Logic Family | CMOS | — |
| Supply Voltage (VCCINT) | 5 V | 5 V (5% tolerance) |
| MultiVolt I/O Voltage | 3.3 V / 5 V | — |
| 封装 | TQFP-100 (C100) | 100-pin PQFP (Plastic Quad Flat Pack) |
| 引脚数量 | 100 | — |
| 安装类型 | Surface Mount | Surface Mount |
| Programmability | In-System Programmable (JTAG, IEEE 1149.1), EEPROM | — |
| 工作温度 | 0C to +70C (commercial) | 0C to +70C (Commercial) |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance status not in provided data] | Non-compliant (SnPb lead finish - legacy PQFP) |
| Macrocells | — | 128 |
| Logic Array Blocks (LABs) | — | 4 (16 macrocells each) |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fMAX value] |
| Typical Gate Count | — | 2,500 gates |
| Programming Technology | — | EEPROM (in-system programmable via JTAG) |
| JTAG Interface | — | IEEE Std. 1149.1 compliant |
| MSL 等级 | — | 3 (168 hours) |