EPM7160SLC84-10 vs EPM7160SLC84-10N Vergleich
Detaillierter Direktvergleich von EPM7160SLC84-10 von Altera und EPM7160SLC84-10N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM7160SLC84-10 | EPM7160SLC84-10N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $35,77 | $9,85 |
| Family | MAX 7000S | MAX 7000S |
| Macrocells | 160 | — |
| Logic Array Blocks (LABs) | 4 | 4 |
| Maximum User I/O Pins | 64 | — |
| Usable Gates | 3,200 | 3,200 gates |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Operating Frequency | 100 MHz | 100 MHz |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG, 5.0 V) | — |
| Technology | EEPROM-based CMOS | — |
| Gehäuse | 84-Pin PLCC (J-Lead) | 84-pin PLCC (J-lead, surface mount) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | 0C to +70C (Commercial) | — |
| JTAG Boundary Scan | Yes (IEEE Std. 1149.1 compliant) | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | — |
| Logic Elements / Macrocells | — | 160 macrocells |
| User I/O Pins | — | 64 (also reported as 60 or 36 depending on variant) |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Counter Speed (fCNT) | — | up to 175.4 MHz |
| Supply Voltage - Core (VCC) | — | 5.0 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V or 5.0 V |
| Configuration Memory | — | EEPROM (non-volatile) |
| In-System Programming | — | Yes, via IEEE Std. 1149.1 JTAG |
| Program / Erase Cycles | — | 100 minimum |
| Data Retention | — | 20 years minimum |
| Operating Temperature Grade | — | Commercial (0C to +70C) |
| Lead-Free / RoHS | — | Yes (-N suffix indicates lead-free) |