EPM7160SLC84-10 vs EPM7160SLC84-10N Comparison
Detailed side-by-side comparison of EPM7160SLC84-10 by Altera and EPM7160SLC84-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM7160SLC84-10 | EPM7160SLC84-10N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $35.77 | $9.85 |
| Family | MAX 7000S | MAX 7000S |
| Macrocells | 160 | β |
| Logic Array Blocks (LABs) | 4 | 4 |
| Maximum User I/O Pins | 64 | β |
| Usable Gates | 3,200 | 3,200 gates |
| Propagation Delay (tPD) | 10 ns | β |
| Maximum Operating Frequency | 100 MHz | 100 MHz |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | β |
| In-System Programmability | Yes (IEEE 1149.1 JTAG, 5.0 V) | β |
| Technology | EEPROM-based CMOS | β |
| Package | 84-Pin PLCC (J-Lead) | 84-pin PLCC (J-lead, surface mount) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0C to +70C (Commercial) | β |
| JTAG Boundary Scan | Yes (IEEE Std. 1149.1 compliant) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| Logic Elements / Macrocells | β | 160 macrocells |
| User I/O Pins | β | 64 (also reported as 60 or 36 depending on variant) |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| Counter Speed (fCNT) | β | up to 175.4 MHz |
| Supply Voltage - Core (VCC) | β | 5.0 V |
| I/O Supply Voltage (VCCIO) | β | 3.3 V or 5.0 V |
| Configuration Memory | β | EEPROM (non-volatile) |
| In-System Programming | β | Yes, via IEEE Std. 1149.1 JTAG |
| Program / Erase Cycles | β | 100 minimum |
| Data Retention | β | 20 years minimum |
| Operating Temperature Grade | β | Commercial (0C to +70C) |
| Lead-Free / RoHS | β | Yes (-N suffix indicates lead-free) |