EPM7160SLC84-10 vs EPM7160SLC84-10N Comparaison
Comparaison détaillée côte à côte de EPM7160SLC84-10 par Altera et EPM7160SLC84-10N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM7160SLC84-10 | EPM7160SLC84-10N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $35,77 | $9,85 |
| Family | MAX 7000S | MAX 7000S |
| Macrocells | 160 | — |
| Logic Array Blocks (LABs) | 4 | 4 |
| Maximum User I/O Pins | 64 | — |
| Usable Gates | 3,200 | 3,200 gates |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Operating Frequency | 100 MHz | 100 MHz |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG, 5.0 V) | — |
| Technology | EEPROM-based CMOS | — |
| Boîtier | 84-Pin PLCC (J-Lead) | 84-pin PLCC (J-lead, surface mount) |
| Type de montage | Surface Mount | Surface Mount |
| Température de fonctionnement | 0C to +70C (Commercial) | — |
| JTAG Boundary Scan | Yes (IEEE Std. 1149.1 compliant) | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | — |
| Logic Elements / Macrocells | — | 160 macrocells |
| User I/O Pins | — | 64 (also reported as 60 or 36 depending on variant) |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Counter Speed (fCNT) | — | up to 175.4 MHz |
| Supply Voltage - Core (VCC) | — | 5.0 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V or 5.0 V |
| Configuration Memory | — | EEPROM (non-volatile) |
| In-System Programming | — | Yes, via IEEE Std. 1149.1 JTAG |
| Program / Erase Cycles | — | 100 minimum |
| Data Retention | — | 20 years minimum |
| Operating Temperature Grade | — | Commercial (0C to +70C) |
| Lead-Free / RoHS | — | Yes (-N suffix indicates lead-free) |