EPM7160SQC160-10 vs EPM7160STI100-10 Vergleich

Detaillierter Direktvergleich von EPM7160SQC160-10 von Altera und EPM7160STI100-10 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM7160SQC160-10 EPM7160STI100-10
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $12,20 $90,43
Family MAX 7000S MAX 7000S
Macro Cells 160 —
Logic Elements / Gates 3,200 usable gates —
User I/Os 104 84
Logic Array Blocks (LABs) 10 —
Maximum Operating Frequency 100 MHz 100 MHz
Pin-to-Pin Propagation Delay (tPD) 10 ns —
Supply Voltage (VCCINT) 5.0 V —
I/O Voltage Tolerance 5.0 V —
Programming Technology EEPROM, in-system programmable —
JTAG Support IEEE 1149.1 (boundary-scan + ISP) —
Gehäuse PQFP-160 (SQC160) TQFP-100 (100-pin Thin Quad Flat Pack)
Betriebstemperatur 0 C to +70 C (commercial) -40 C to +85 C (Industrial)
Logic Family CMOS —
Montageart Surface Mount Surface Mount
Process Technology CMOS, EEPROM-based —
RoHS-Status unknown [DATA_NEEDED: RoHS status - not explicitly stated in provided data]
Lead-Free unknown [DATA_NEEDED: lead-free status]
Macrocells — 160
Usable Gates — 3,200
Logic Elements / Blocks — 16 Logic Array Blocks (LABs)
Propagation Delay (tPD) — 10 ns
Internal Supply Voltage — 4.75 V to 5.25 V
I/O Supply Voltage — 5.0 V
Programmable Type — In-System Programmable (EEPROM)
JTAG / Boundary Scan — IEEE Std. 1149.1 compliant
PCI Compliance — PCI Local Bus Specification Rev. 2.2 (for -10 speed grade)
MSL-Level — [DATA_NEEDED: MSL rating]

Datenblätter & Ressourcen

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