EPM7160SQC160-10 vs EPM7160STI100-10 Comparison
Detailed side-by-side comparison of EPM7160SQC160-10 by Altera and EPM7160STI100-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7160SQC160-10
EPM7160SQC160-10 - MAX 7000S CPLD, 160 Macro Cells, 100MHz, PQFP-160 | Intel / Altera
EPM7160SQC160-10 ObsoleteAltera
EPM7160STI100-10
EPM7160STI100-10 - MAX 7000S CPLD, 160 Macrocells, 100MHz | Altera
EPM7160STI100-10 ObsoleteSpecification Comparison
| Parameter | EPM7160SQC160-10 | EPM7160STI100-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $12.20 | $90.43 |
| Family | MAX 7000S | MAX 7000S |
| Macro Cells | 160 | β |
| Logic Elements / Gates | 3,200 usable gates | β |
| User I/Os | 104 | 84 |
| Logic Array Blocks (LABs) | 10 | β |
| Maximum Operating Frequency | 100 MHz | 100 MHz |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns | β |
| Supply Voltage (VCCINT) | 5.0 V | β |
| I/O Voltage Tolerance | 5.0 V | β |
| Programming Technology | EEPROM, in-system programmable | β |
| JTAG Support | IEEE 1149.1 (boundary-scan + ISP) | β |
| Package | PQFP-160 (SQC160) | TQFP-100 (100-pin Thin Quad Flat Pack) |
| Operating Temperature | 0 C to +70 C (commercial) | -40 C to +85 C (Industrial) |
| Logic Family | CMOS | β |
| Mounting Type | Surface Mount | Surface Mount |
| Process Technology | CMOS, EEPROM-based | β |
| RoHS Status | unknown | [DATA_NEEDED: RoHS status - not explicitly stated in provided data] |
| Lead-Free | unknown | [DATA_NEEDED: lead-free status] |
| Macrocells | β | 160 |
| Usable Gates | β | 3,200 |
| Logic Elements / Blocks | β | 16 Logic Array Blocks (LABs) |
| Propagation Delay (tPD) | β | 10 ns |
| Internal Supply Voltage | β | 4.75 V to 5.25 V |
| I/O Supply Voltage | β | 5.0 V |
| Programmable Type | β | In-System Programmable (EEPROM) |
| JTAG / Boundary Scan | β | IEEE Std. 1149.1 compliant |
| PCI Compliance | β | PCI Local Bus Specification Rev. 2.2 (for -10 speed grade) |
| MSL Level | β | [DATA_NEEDED: MSL rating] |