EPM7256EGC192-12 vs EPM7256EGI192-15 Vergleich
Detaillierter Direktvergleich von EPM7256EGC192-12 von Intel und EPM7256EGI192-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM7256EGC192-12 | EPM7256EGI192-15 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $17,85 | $52,00 |
| Family | MAX 7000 | MAX 7000 |
| Device Logic Cells | 256 macrocells | — |
| Usable Gates | 5,000 | 5,000 |
| Propagation Delay (tPD) | 12 ns | — |
| Maximum Operating Frequency | 90.9 MHz | 76.9 MHz |
| User I/O Pins | 164 | 192 |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| Gehäuse | 192-pin CPGA (Ceramic Pin Grid Array) | 192-pin CPGA (Ceramic Pin Grid Array) |
| Montageart | Through Hole (PGA socket) | Through-Hole (Socket) |
| Technology | CMOS, EEPROM-based | — |
| Betriebstemperatur | 0C to +70C (commercial) | — |
| Programmable Interface | JTAG (IEEE 1149.1) / ISP | — |
| Logic Blocks (LABs) | 16 | — |
| Macrocells per LAB | 16 | — |
| RoHS-Status | Compliant | Non-compliant (ceramic CPGA, contains lead) |
| Lead-Free | Yes | — |
| JEDEC Package Code | S-CPGA-P192 | — |
| Series | — | MAX 7000E |
| Macro Cells | — | 256 |
| Logic Array Blocks (LABs) | — | 16 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Dedicated Input Pins | — | 12 |
| Programmable Power Mode | — | Yes (per-macrocell) |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Configuration Memory | — | EEPROM (non-volatile) |
| Operating Temperature Grade | — | Industrial (-40C to +85C) |