EPM7256EGC192-12 vs EPM7256EGI192-15 对比
详细并排对比 EPM7256EGC192-12 出自 Intel 和 EPM7256EGI192-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM7256EGC192-12 | EPM7256EGI192-15 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $17.85 | $52.00 |
| Family | MAX 7000 | MAX 7000 |
| Device Logic Cells | 256 macrocells | — |
| Usable Gates | 5,000 | 5,000 |
| Propagation Delay (tPD) | 12 ns | — |
| Maximum Operating Frequency | 90.9 MHz | 76.9 MHz |
| User I/O Pins | 164 | 192 |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| 封装 | 192-pin CPGA (Ceramic Pin Grid Array) | 192-pin CPGA (Ceramic Pin Grid Array) |
| 安装类型 | Through Hole (PGA socket) | Through-Hole (Socket) |
| Technology | CMOS, EEPROM-based | — |
| 工作温度 | 0C to +70C (commercial) | — |
| Programmable Interface | JTAG (IEEE 1149.1) / ISP | — |
| Logic Blocks (LABs) | 16 | — |
| Macrocells per LAB | 16 | — |
| RoHS 状态 | Compliant | Non-compliant (ceramic CPGA, contains lead) |
| Lead-Free | Yes | — |
| JEDEC Package Code | S-CPGA-P192 | — |
| Series | — | MAX 7000E |
| Macro Cells | — | 256 |
| Logic Array Blocks (LABs) | — | 16 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Dedicated Input Pins | — | 12 |
| Programmable Power Mode | — | Yes (per-macrocell) |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Configuration Memory | — | EEPROM (non-volatile) |
| Operating Temperature Grade | — | Industrial (-40C to +85C) |