EPM7256SQC208-15N vs EPM7256SQC208-7 Vergleich
Detaillierter Direktvergleich von EPM7256SQC208-15N von Altera und EPM7256SQC208-7 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM7256SQC208-15N | EPM7256SQC208-7 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $0,00 |
| Series | MAX 7000S | — |
| Macrocells | 256 | 256 |
| User I/O Pins | 164 | 164 |
| Pin-to-Pin Delay | 15 ns (speed grade -15) | — |
| Versorgungsspannung | 5 V | — |
| Gehäuse | 208-pin PQFP | 208-pin PQFP (28 x 28 mm, 0.5 mm pitch) |
| Montageart | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | — |
| JTAG Interface | IEEE 1149.1 boundary-scan | — |
| In-System Programmability | Yes (ISP) | Yes (IEEE 1149.1 JTAG) |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | — |
| RoHS-Status | Lead free / RoHS Compliant | [DATA_NEEDED: RoHS status] |
| Logic Array Blocks | 16 macrocells per LAB | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Speed Grade | -15 | -7 (7.5 ns) |
| Product Category | CPLD - Complex Programmable Logic Devices | — |
| Manufacturer | Altera (Intel Programmable Solutions Group) | — |
| Device Family | — | MAX 7000S (EPM7256S) |
| Usable Gates | — | 5,000 |
| Propagation Delay (tPD) | — | 7.5 ns |
| Maximum Operating Frequency (fMAX) | — | 128.2 MHz |
| Supply Voltage (VCC) | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| Betriebstemperaturbereich | — | Commercial (0C to +70C) |
| Minimum DC Input Voltage | — | -0.5 V |
| Input Undershoot Tolerance | — | -2.0 V for <100 mA, <20 ns |
| MSL-Level | — | [DATA_NEEDED: MSL level] |
| Logic Levels | — | 5.0 V CMOS/TTL compatible |