EPM7256SRC208-15N vs EPM7256SRC208-10 Vergleich

Detaillierter Direktvergleich von EPM7256SRC208-15N von Altera und EPM7256SRC208-10 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Altera
EPM7256SRC208-15N EPM7256SRC208-15N - MAX 7000S CPLD 256 Macro | Altera

EPM7256SRC208-15N - MAX 7000S CPLD 256 Macro | Altera

EPM7256SRC208-15N Obsolete

Spezifikationsvergleich

Parameter EPM7256SRC208-15N EPM7256SRC208-10
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $27,20 $27,20
Series MAX 7000S —
Macrocells 256 —
Usable Gates 5,000 —
User I/O Pins 164 —
Logic Array Blocks (LABs) 16 —
Pin-to-Pin Delay (tPD) 15 ns —
Maximum Counter Frequency 76.9 MHz —
Versorgungsspannung 5 V —
Configuration Memory EEPROM (non-volatile) —
Gehäuse 208-pin RQFP (PowerQuad Flat Pack) 208-pin RQFP (BFQFP) exposed pad, 28x28 mm
Montageart Surface Mount Surface Mount
Betriebstemperatur 0C to +70C (commercial) 0C to +70C (TA, commercial)
In-System Programmability Yes (IEEE 1149.1 JTAG) —
I/O Standard 5 V TTL/CMOS compatible —
RoHS-Status Compliant (N suffix) [DATA_NEEDED: RoHS status]
Lead Free Yes (N suffix) —
MSL-Level [DATA_NEEDED: MSL level] —
Number of Terminals 208 —
Family — MAX 7000S
Device Type — CPLD (Complex Programmable Logic Device)
Number of Macrocells — 256
Number of Logic Array Blocks (LABs) — 16
Number of Gates — 5000
Number of User I/O Pins — 164
Maximum Propagation Delay (tPD) — 10 ns
Maximum Operating Frequency — 100 MHz
Supply Voltage (Internal) — 4.75 V to 5.25 V
Programmable Type — In System Programmable (ISP, JTAG)
Configuration Technology — EEPROM
Terminal Form — Gull Wing
Package Shape — Square
Product Status — Obsolete

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