EPM9320ALI84-10N vs EPM9320LC84-10 Vergleich

Detaillierter Direktvergleich von EPM9320ALI84-10N von Altera und EPM9320LC84-10 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM9320ALI84-10N EPM9320LC84-10
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $21,95 $84,96
Family MAX 9000 MAX 9000 EPLD
Device Type CPLD (Complex Programmable Logic Device) —
Architecture MAX (Multiple Array MatriX), 3rd generation —
Process Technology CMOS EEPROM 0.7 µm CMOS EEPROM/UV-EPROM
Usable Gates 6,000 to 12,000 6000 (typical)
Macrocells 320 320
Logic Array Blocks (LABs) 20 16
User I/O Pins 56 —
Pin-to-Pin Delay 10 ns —
Maximum Counter Frequency 144.9 MHz —
VCCINT (Core Supply) 5.0 V —
VCCIO (I/O Supply) 3.3 V or 5.0 V —
Input Logic Levels TTL-compatible (at 5.0 V VCCINT) —
In-System Programmability Yes (IEEE Std. 1149.1 JTAG) —
Gehäuse 84-pin PLCC (J-lead, 1.270 mm pitch) 84-pin PLCC (JEDEC MO-047)
Montageart Surface Mount (PLCC socket compatible) Surface Mount (PLCC socket also common)
Betriebstemperatur -40C to +85C (industrial) 0C to +70C (commercial) [DATA_NEEDED: exact grade suffix]
Configuration Memory EEPROM, non-volatile —
Device — EPM9320
Maximum User I/O Pins — 168 (varies by package)
Pin-to-Pin Logic Delay (tPD) — 10 ns
Maximum Frequency (fCNT) — [DATA_NEEDED: fCNT in MHz]
Supply Voltage (VCC) — 5.0 V (typical, see datasheet)
Programming Interface — JTAG (IEEE 1149.1) boundary-scan, Altera ByteBlaster compatible
Configuration — Non-volatile EEPROM (instant-on, no boot PROM)
RoHS-Status — ROHS3 Compliant (per fpgalink listing)
Feuchtigkeitsempfindlichkeitsgrad (MSL) — MSL-3, 168 hours (per fpgalink listing)
Manufacturer Lead Time — 1-7 days (per fpgalink listing)

Datenblätter & Ressourcen

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