EPM9320ALI84-10N vs EPM9320LC84-10 比較
詳細な並列比較: EPM9320ALI84-10N メーカー: Altera および EPM9320LC84-10 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM9320ALI84-10N | EPM9320LC84-10 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $21.95 | $84.96 |
| Family | MAX 9000 | MAX 9000 EPLD |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Architecture | MAX (Multiple Array MatriX), 3rd generation | — |
| Process Technology | CMOS EEPROM | 0.7 µm CMOS EEPROM/UV-EPROM |
| Usable Gates | 6,000 to 12,000 | 6000 (typical) |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 20 | 16 |
| User I/O Pins | 56 | — |
| Pin-to-Pin Delay | 10 ns | — |
| Maximum Counter Frequency | 144.9 MHz | — |
| VCCINT (Core Supply) | 5.0 V | — |
| VCCIO (I/O Supply) | 3.3 V or 5.0 V | — |
| Input Logic Levels | TTL-compatible (at 5.0 V VCCINT) | — |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) | — |
| パッケージ | 84-pin PLCC (J-lead, 1.270 mm pitch) | 84-pin PLCC (JEDEC MO-047) |
| 実装タイプ | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket also common) |
| 動作温度 | -40C to +85C (industrial) | 0C to +70C (commercial) [DATA_NEEDED: exact grade suffix] |
| Configuration Memory | EEPROM, non-volatile | — |
| Device | — | EPM9320 |
| Maximum User I/O Pins | — | 168 (varies by package) |
| Pin-to-Pin Logic Delay (tPD) | — | 10 ns |
| Maximum Frequency (fCNT) | — | [DATA_NEEDED: fCNT in MHz] |
| Supply Voltage (VCC) | — | 5.0 V (typical, see datasheet) |
| Programming Interface | — | JTAG (IEEE 1149.1) boundary-scan, Altera ByteBlaster compatible |
| Configuration | — | Non-volatile EEPROM (instant-on, no boot PROM) |
| RoHS ステータス | — | ROHS3 Compliant (per fpgalink listing) |
| 湿気感度レベル（MSL） | — | MSL-3, 168 hours (per fpgalink listing) |
| Manufacturer Lead Time | — | 1-7 days (per fpgalink listing) |