EPM9320ALI84-10N vs EPM9320LC84-10 비교

다음의 상세 나란히 비교: EPM9320ALI84-10N 제조: Altera 및 EPM9320LC84-10 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM9320ALI84-10N EPM9320LC84-10
브랜드 Altera Intel
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete NRND
재고 상태 In Stock In Stock
단가 (USD) $21.95 $84.96
Family MAX 9000 MAX 9000 EPLD
Device Type CPLD (Complex Programmable Logic Device) —
Architecture MAX (Multiple Array MatriX), 3rd generation —
Process Technology CMOS EEPROM 0.7 µm CMOS EEPROM/UV-EPROM
Usable Gates 6,000 to 12,000 6000 (typical)
Macrocells 320 320
Logic Array Blocks (LABs) 20 16
User I/O Pins 56 —
Pin-to-Pin Delay 10 ns —
Maximum Counter Frequency 144.9 MHz —
VCCINT (Core Supply) 5.0 V —
VCCIO (I/O Supply) 3.3 V or 5.0 V —
Input Logic Levels TTL-compatible (at 5.0 V VCCINT) —
In-System Programmability Yes (IEEE Std. 1149.1 JTAG) —
패키지 84-pin PLCC (J-lead, 1.270 mm pitch) 84-pin PLCC (JEDEC MO-047)
실장 유형 Surface Mount (PLCC socket compatible) Surface Mount (PLCC socket also common)
동작 온도 -40C to +85C (industrial) 0C to +70C (commercial) [DATA_NEEDED: exact grade suffix]
Configuration Memory EEPROM, non-volatile —
Device — EPM9320
Maximum User I/O Pins — 168 (varies by package)
Pin-to-Pin Logic Delay (tPD) — 10 ns
Maximum Frequency (fCNT) — [DATA_NEEDED: fCNT in MHz]
Supply Voltage (VCC) — 5.0 V (typical, see datasheet)
Programming Interface — JTAG (IEEE 1149.1) boundary-scan, Altera ByteBlaster compatible
Configuration — Non-volatile EEPROM (instant-on, no boot PROM)
RoHS 상태 — ROHS3 Compliant (per fpgalink listing)
습도 민감도 레벨 (MSL) — MSL-3, 168 hours (per fpgalink listing)
Manufacturer Lead Time — 1-7 days (per fpgalink listing)

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