EPM9320GC280-20 vs EPM9560GC280-20 Vergleich

Detaillierter Direktvergleich von EPM9320GC280-20 von Altera und EPM9560GC280-20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM9320GC280-20 EPM9560GC280-20
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $67,00 $360,00
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 320 560
Usable Gates 6000 (approx.) 12,000
Logic Array Blocks (LABs) 20 (16 macrocells each, typical for MAX 9000) —
Maximum Operating Frequency 100 MHz (internal counter) —
Propagation Delay (tpd) 23 ns (approx., -20 speed grade) —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) —
Technology CMOS EEPROM —
In-System Programmability Yes (5.0-V ISP via JTAG) —
JTAG Support IEEE Std. 1149.1 compliant —
Gehäuse 280-pin Ceramic Pin Grid Array (CPGA) 280-pin CPGA (Ceramic Pin Grid Array)
Betriebstemperatur [DATA_NEEDED: operating temperature grade] [DATA_NEEDED: commercial/industrial/military grade]
Montageart Through-Hole (PGA socket) Through-Hole (CPGA socket)
RoHS-Status unknown [DATA_NEEDED: CPGA package historically contains Pb; likely non-compliant]
Configuration Memory EEPROM (non-volatile, instant-on) —
Maximum User I/O — 212
Pin-to-Pin Delay — 20 ns (speed grade -20)
Counter Frequency (max) — 100 MHz
Supply Voltage (VCCINT) — 4.75 V to 5.25 V (5.0 V nominal)
I/O Voltage — 3.3 V or 5.0 V configurable
Process Technology — CMOS EEPROM
In-System Programming — Yes, via IEEE 1149.1 JTAG

Datenblätter & Ressourcen

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