EPM9320GC280-20 vs EPM9560GC280-20 Comparação
Comparação detalhada lado a lado de EPM9320GC280-20 por Altera e EPM9560GC280-20 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPM9320GC280-20 | EPM9560GC280-20 |
|---|---|---|
| Marca | Altera | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $67,00 | $360,00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 560 |
| Usable Gates | 6000 (approx.) | 12,000 |
| Logic Array Blocks (LABs) | 20 (16 macrocells each, typical for MAX 9000) | — |
| Maximum Operating Frequency | 100 MHz (internal counter) | — |
| Propagation Delay (tpd) | 23 ns (approx., -20 speed grade) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (5.0-V ISP via JTAG) | — |
| JTAG Support | IEEE Std. 1149.1 compliant | — |
| Encapsulamento | 280-pin Ceramic Pin Grid Array (CPGA) | 280-pin CPGA (Ceramic Pin Grid Array) |
| Temperatura de operação | [DATA_NEEDED: operating temperature grade] | [DATA_NEEDED: commercial/industrial/military grade] |
| Tipo de montagem | Through-Hole (PGA socket) | Through-Hole (CPGA socket) |
| Status RoHS | unknown | [DATA_NEEDED: CPGA package historically contains Pb; likely non-compliant] |
| Configuration Memory | EEPROM (non-volatile, instant-on) | — |
| Maximum User I/O | — | 212 |
| Pin-to-Pin Delay | — | 20 ns (speed grade -20) |
| Counter Frequency (max) | — | 100 MHz |
| Supply Voltage (VCCINT) | — | 4.75 V to 5.25 V (5.0 V nominal) |
| I/O Voltage | — | 3.3 V or 5.0 V configurable |
| Process Technology | — | CMOS EEPROM |
| In-System Programming | — | Yes, via IEEE 1149.1 JTAG |