EPM9320LI84-20N vs EPM9320ALI84-10N Vergleich
Detaillierter Direktvergleich von EPM9320LI84-20N von Altera und EPM9320ALI84-10N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9320LI84-20N | EPM9320ALI84-10N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $21,95 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 to 12,000 | 6,000 to 12,000 |
| User I/O Pins | 60 | 56 |
| Total Pins | 84 | — |
| Gehäuse | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) | 84-pin PLCC (J-lead, 1.270 mm pitch) |
| Propagation Delay (tPD) | 20 ns (speed grade -20) | — |
| Pin-to-Pin Delay | 16 ns (per DigChip spec block) | 10 ns |
| Maximum Counter Frequency | 118 MHz | 144.9 MHz |
| Logic Family | CMOS, EEPROM-based | — |
| Versorgungsspannung | 5.0 V | — |
| Betriebstemperatur | 0 C to +70 C (commercial) | -40C to +85C (industrial) |
| Programming Interface | IEEE 1149.1 JTAG, in-system programmable | — |
| Architecture | Multiple Array MatriX (MAX) - third generation | MAX (Multiple Array MatriX), 3rd generation |
| Process Technology | Advanced CMOS EEPROM | CMOS EEPROM |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | — |
| Logic Array Blocks (LABs) | — | 20 |
| VCCINT (Core Supply) | — | 5.0 V |
| VCCIO (I/O Supply) | — | 3.3 V or 5.0 V |
| Input Logic Levels | — | TTL-compatible (at 5.0 V VCCINT) |
| In-System Programmability | — | Yes (IEEE Std. 1149.1 JTAG) |
| Montageart | — | Surface Mount (PLCC socket compatible) |
| Configuration Memory | — | EEPROM, non-volatile |