EPM9320LI84-20N vs EPM9320ALI84-10N 비교
다음의 상세 나란히 비교: EPM9320LI84-20N 제조: Altera 및 EPM9320ALI84-10N 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM9320LI84-20N | EPM9320ALI84-10N |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.75 | $21.95 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 to 12,000 | 6,000 to 12,000 |
| User I/O Pins | 60 | 56 |
| Total Pins | 84 | — |
| 패키지 | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) | 84-pin PLCC (J-lead, 1.270 mm pitch) |
| Propagation Delay (tPD) | 20 ns (speed grade -20) | — |
| Pin-to-Pin Delay | 16 ns (per DigChip spec block) | 10 ns |
| Maximum Counter Frequency | 118 MHz | 144.9 MHz |
| Logic Family | CMOS, EEPROM-based | — |
| 공급 전압 | 5.0 V | — |
| 동작 온도 | 0 C to +70 C (commercial) | -40C to +85C (industrial) |
| Programming Interface | IEEE 1149.1 JTAG, in-system programmable | — |
| Architecture | Multiple Array MatriX (MAX) - third generation | MAX (Multiple Array MatriX), 3rd generation |
| Process Technology | Advanced CMOS EEPROM | CMOS EEPROM |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance status] | — |
| Logic Array Blocks (LABs) | — | 20 |
| VCCINT (Core Supply) | — | 5.0 V |
| VCCIO (I/O Supply) | — | 3.3 V or 5.0 V |
| Input Logic Levels | — | TTL-compatible (at 5.0 V VCCINT) |
| In-System Programmability | — | Yes (IEEE Std. 1149.1 JTAG) |
| 실장 유형 | — | Surface Mount (PLCC socket compatible) |
| Configuration Memory | — | EEPROM, non-volatile |