EPM9320RC208-20N vs EPM9320RC208-15 Vergleich
Detaillierter Direktvergleich von EPM9320RC208-20N von Altera und EPM9320RC208-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9320RC208-20N | EPM9320RC208-15 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $0,00 |
| Device Family | MAX 9000 | MAX 9000 |
| Logic Type | Complex Programmable Logic Device (CPLD) | — |
| Usable Gates | 6,000 | 6,000 |
| Macro Cells | 320 | 320 |
| Logic Array Blocks | 20 | [DATA_NEEDED: LAB count] |
| Maximum Pin-to-Pin Delay (tPD) | 20 ns | — |
| Maximum Operating Frequency | 100 MHz | — |
| Versorgungsspannung | 5.0 V | 5.0 V |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes (ISP via JTAG) |
| User I/O Pins | 168 | — |
| Gehäuse | 208-pin RQFP (PowerQuad II) | 208-pin RQFP (Power QFP) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| Pin-to-Pin Propagation Delay | — | 15 ns (speed grade -15) |
| Maximale Taktfrequenz | — | 117.6 MHz |
| Configuration Technology | — | EEPROM-based (non-volatile) |
| JTAG Interface | — | IEEE Std. 1149.1 |
| Package Type | — | 208-BFQFP Exposed Pad |
| Number of I/O Pins | — | [DATA_NEEDED: user I/O count] |
| Lebenszyklusstatus | — | Obsolete (PDN0706, 2007) |