EPM9320RC208-20N vs EPM9320RC208-15 Comparison
Detailed side-by-side comparison of EPM9320RC208-20N by Altera and EPM9320RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320RC208-20N | EPM9320RC208-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | MAX 9000 | MAX 9000 |
| Logic Type | Complex Programmable Logic Device (CPLD) | — |
| Usable Gates | 6,000 | 6,000 |
| Macro Cells | 320 | 320 |
| Logic Array Blocks | 20 | [DATA_NEEDED: LAB count] |
| Maximum Pin-to-Pin Delay (tPD) | 20 ns | — |
| Maximum Operating Frequency | 100 MHz | — |
| Supply Voltage | 5.0 V | 5.0 V |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes (ISP via JTAG) |
| User I/O Pins | 168 | — |
| Package | 208-pin RQFP (PowerQuad II) | 208-pin RQFP (Power QFP) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| MSL Level | [DATA_NEEDED: MSL level] | — |
| Pin-to-Pin Propagation Delay | — | 15 ns (speed grade -15) |
| Maximum Clock Frequency | — | 117.6 MHz |
| Configuration Technology | — | EEPROM-based (non-volatile) |
| JTAG Interface | — | IEEE Std. 1149.1 |
| Package Type | — | 208-BFQFP Exposed Pad |
| Number of I/O Pins | — | [DATA_NEEDED: user I/O count] |
| Lifecycle Status | — | Obsolete (PDN0706, 2007) |