EPM9320RI208-10N vs EPM9320RI208-20 Vergleich
Detaillierter Direktvergleich von EPM9320RI208-10N von Altera und EPM9320RI208-20 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9320RI208-10N | EPM9320RI208-20 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $27,20 | $18,95 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | Complex Programmable Logic Device (CPLD) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 6,000 | 6,000 |
| Macro Cells | 320 | — |
| Logic Array Blocks (LABs) | 20 | — |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns | — |
| Maximum System Clock Frequency | 100 MHz | — |
| Versorgungsspannung | 5 V | — |
| I/O Voltage | 5 V | — |
| User I/O Pins | 160 | [DATA_NEEDED: I/O pin count for 208-pin RQFP] |
| Gehäuse | 208-pin RQFP (PowerQuad II) | 208-pin RQFP (Power Quad Flat Pack) |
| Montageart | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (JTAG/ISP) | Yes - IEEE 1149.1 JTAG, 5.0-V ISP |
| Betriebstemperaturbereich | -40C to +85C (industrial) | — |
| RoHS-Status | Compliant (N suffix = lead-free) | [DATA_NEEDED: RoHS compliance] |
| Lead Finish | Lead-free (matte tin) | — |
| MSL-Level | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL rating] |
| Macrocells | — | 320 |
| Propagation Delay (tPD) | — | 20 ns |
| Maximum Operating Frequency | — | 100 MHz |
| Supply Voltage (VCC) | — | 5.0 V |
| Logic Elements / LABs | — | 20 Logic Array Blocks (16 macro cells each) |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA) |
| Dedicated Input Pins | — | 4 (low-skew global) |
| Operating Temperature Grade | — | Industrial |
| Technology | — | CMOS EEPROM |