EPM9320RI208-10N vs EPM9320RI208-20 比較
詳細な並列比較: EPM9320RI208-10N メーカー: Altera および EPM9320RI208-20 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM9320RI208-10N | EPM9320RI208-20 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $27.20 | $18.95 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | Complex Programmable Logic Device (CPLD) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 6,000 | 6,000 |
| Macro Cells | 320 | — |
| Logic Array Blocks (LABs) | 20 | — |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns | — |
| Maximum System Clock Frequency | 100 MHz | — |
| 電源電圧 | 5 V | — |
| I/O Voltage | 5 V | — |
| User I/O Pins | 160 | [DATA_NEEDED: I/O pin count for 208-pin RQFP] |
| パッケージ | 208-pin RQFP (PowerQuad II) | 208-pin RQFP (Power Quad Flat Pack) |
| 実装タイプ | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (JTAG/ISP) | Yes - IEEE 1149.1 JTAG, 5.0-V ISP |
| 動作温度範囲 | -40C to +85C (industrial) | — |
| RoHS ステータス | Compliant (N suffix = lead-free) | [DATA_NEEDED: RoHS compliance] |
| Lead Finish | Lead-free (matte tin) | — |
| MSLレベル | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL rating] |
| Macrocells | — | 320 |
| Propagation Delay (tPD) | — | 20 ns |
| Maximum Operating Frequency | — | 100 MHz |
| Supply Voltage (VCC) | — | 5.0 V |
| Logic Elements / LABs | — | 20 Logic Array Blocks (16 macro cells each) |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA) |
| Dedicated Input Pins | — | 4 (low-skew global) |
| Operating Temperature Grade | — | Industrial |
| Technology | — | CMOS EEPROM |