EPM9400LC84-20 vs EPM7160SLC84-15 Vergleich

Detaillierter Direktvergleich von EPM9400LC84-20 von Altera und EPM7160SLC84-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM9400LC84-20 EPM7160SLC84-15
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $38,50 $10,80
Family MAX 9000 MAX 7000
Device Type CPLD (Complex Programmable Logic Device) —
Architecture Multiple Array Matrix (MAX), 3rd generation, EEPROM-based —
Macrocells 400 160
Usable Gates 8,000 (6,000 to 12,000 typical range) 3,200
Flip-Flops 580 —
Maximum User I/O 55 —
Pin-to-Pin Propagation Delay 20 ns (speed grade -20) —
Maximum Counter Frequency 144 MHz —
Supply Voltage (VCCINT) 5 V —
I/O Voltage (VCCIO) 3.3 V or 5 V (configurable) —
In-System Programming Yes (IEEE 1149.1 JTAG) —
Gehäuse 84-pin PLCC (Plastic Leaded Chip Carrier) —
Process Technology CMOS EEPROM —
Betriebstemperatur Commercial (0C to +70C) - assumed from -20 speed grade 0 C to 70 C
Montageart Surface Mount (PLCC socket or SMT land pattern) Surface Mount (PLCC socket or direct solder)
RoHS-Status [DATA_NEEDED: RoHS status] Not RoHS compliant (contains lead, SnPb finish typical)
Maximum Propagation Delay — 15 ns
Maximum User I/O Pins — 64
Supply Voltage (VCCINT/VCIO) — 4.75 V to 5.25 V (5 V nominal)
I/O Logic Level — Configurable 3.3 V or 5 V
Technology — CMOS, EEPROM configuration
Package Type — PLCC-84 (PQCC84, JEDEC S-PQCC-J84)
Terminal Pitch — 1.270 mm
Programming Interface — JTAG (IEEE 1149.1) in-system programmable
Lifecycle — Obsolete / last-time-buy (per Altera/Intel PDN)

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