EPM9400LC84-20 vs EPM7160SLC84-15 Comparison

Detailed side-by-side comparison of EPM9400LC84-20 by Altera and EPM7160SLC84-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9400LC84-20 EPM7160SLC84-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $38.50 $10.80
Family MAX 9000 MAX 7000
Device Type CPLD (Complex Programmable Logic Device) β€”
Architecture Multiple Array Matrix (MAX), 3rd generation, EEPROM-based β€”
Macrocells 400 160
Usable Gates 8,000 (6,000 to 12,000 typical range) 3,200
Flip-Flops 580 β€”
Maximum User I/O 55 β€”
Pin-to-Pin Propagation Delay 20 ns (speed grade -20) β€”
Maximum Counter Frequency 144 MHz β€”
Supply Voltage (VCCINT) 5 V β€”
I/O Voltage (VCCIO) 3.3 V or 5 V (configurable) β€”
In-System Programming Yes (IEEE 1149.1 JTAG) β€”
Package 84-pin PLCC (Plastic Leaded Chip Carrier) β€”
Process Technology CMOS EEPROM β€”
Operating Temperature Commercial (0C to +70C) - assumed from -20 speed grade 0 C to 70 C
Mounting Type Surface Mount (PLCC socket or SMT land pattern) Surface Mount (PLCC socket or direct solder)
RoHS Status [DATA_NEEDED: RoHS status] Not RoHS compliant (contains lead, SnPb finish typical)
Maximum Propagation Delay β€” 15 ns
Maximum User I/O Pins β€” 64
Supply Voltage (VCCINT/VCIO) β€” 4.75 V to 5.25 V (5 V nominal)
I/O Logic Level β€” Configurable 3.3 V or 5 V
Technology β€” CMOS, EEPROM configuration
Package Type β€” PLCC-84 (PQCC84, JEDEC S-PQCC-J84)
Terminal Pitch β€” 1.270 mm
Programming Interface β€” JTAG (IEEE 1149.1) in-system programmable
Lifecycle β€” Obsolete / last-time-buy (per Altera/Intel PDN)

Datasheets & Resources

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