EPM9560GC280-20 vs EPM9560R1208-20 Vergleich

Detaillierter Direktvergleich von EPM9560GC280-20 von Altera und EPM9560R1208-20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM9560GC280-20 EPM9560R1208-20
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $360,00 $22,40
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Usable Gates 12,000 6,000
Macrocells 560 560
Maximum User I/O 212 212
Pin-to-Pin Delay 20 ns (speed grade -20) —
Counter Frequency (max) 100 MHz —
Supply Voltage (VCCINT) 4.75 V to 5.25 V (5.0 V nominal) —
I/O Voltage 3.3 V or 5.0 V configurable —
Process Technology CMOS EEPROM CMOS EEPROM, third-generation MAX architecture
Gehäuse 280-pin CPGA (Ceramic Pin Grid Array) R-1208 (BGA-style fine-pitch)
Betriebstemperatur [DATA_NEEDED: commercial/industrial/military grade] 0C to +70C (commercial)
In-System Programming Yes, via IEEE 1149.1 JTAG —
Montageart Through-Hole (CPGA socket) Surface Mount
RoHS-Status [DATA_NEEDED: CPGA package historically contains Pb; likely non-compliant] [DATA_NEEDED: confirm via current distributor data]
Logic Array Blocks — 52 (typical for 560 macrocells)
Propagation Delay (tPD) — 20 ns
Maximum Frequency (fMAX) — 125 MHz
Supply Voltage (VCCINT/VCCIO) — 5.0 V
Technology — CMOS EEPROM
In-System Programmability — Yes (IEEE 1149.1 JTAG)
Architecture — Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA)
Boundary-Scan Test — JTAG IEEE Std. 1149.1
Configuration Memory — On-chip EEPROM (non-volatile)

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