EPM9560GC280-20 vs EPM9560R1208-20 Comparación
Comparación detallada lado a lado de EPM9560GC280-20 por Altera y EPM9560R1208-20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560GC280-20 | EPM9560R1208-20 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $360,00 | $22,40 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 | 6,000 |
| Macrocells | 560 | 560 |
| Maximum User I/O | 212 | 212 |
| Pin-to-Pin Delay | 20 ns (speed grade -20) | — |
| Counter Frequency (max) | 100 MHz | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) | — |
| I/O Voltage | 3.3 V or 5.0 V configurable | — |
| Process Technology | CMOS EEPROM | CMOS EEPROM, third-generation MAX architecture |
| Encapsulado | 280-pin CPGA (Ceramic Pin Grid Array) | R-1208 (BGA-style fine-pitch) |
| Temperatura de funcionamiento | [DATA_NEEDED: commercial/industrial/military grade] | 0C to +70C (commercial) |
| In-System Programming | Yes, via IEEE 1149.1 JTAG | — |
| Tipo de montaje | Through-Hole (CPGA socket) | Surface Mount |
| Estado RoHS | [DATA_NEEDED: CPGA package historically contains Pb; likely non-compliant] | [DATA_NEEDED: confirm via current distributor data] |
| Logic Array Blocks | — | 52 (typical for 560 macrocells) |
| Propagation Delay (tPD) | — | 20 ns |
| Maximum Frequency (fMAX) | — | 125 MHz |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Architecture | — | Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA) |
| Boundary-Scan Test | — | JTAG IEEE Std. 1149.1 |
| Configuration Memory | — | On-chip EEPROM (non-volatile) |