EPM9560GC280-20N vs EPM9560GC280-15 Vergleich
Detaillierter Direktvergleich von EPM9560GC280-20N von Altera und EPM9560GC280-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 ObsoleteSpezifikationsvergleich
| Parameter | EPM9560GC280-20N | EPM9560GC280-15 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $285,00 | $115,00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EE PLD (CMOS EEPROM-based CPLD) |
| Architecture | Multiple Array MatriX (MAX), 3rd generation | Multiple Array MatriX (MAX) |
| Technology | CMOS EEPROM-based | CMOS EEPROM, 0.5 um process (MAX third-gen) |
| Usable Gates | 6,000 to 12,000 | — |
| Macrocells | 560 | — |
| User I/O Pins | 212 | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Maximum Counter Frequency | 144 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| I/O Voltage | 3.3 V or 5 V (configurable) | — |
| In-System Programmability | Yes (5.0-V ISP via IEEE 1149.1 JTAG) | — |
| Gehäuse | 280-pin CPGA (Ceramic Pin Grid Array) | — |
| Configuration Memory | EEPROM (non-volatile, instant-on) | — |
| PCI Compliance | Yes | — |
| Betriebstemperatur | [DATA_NEEDED: industrial/commercial grade] | — |
| RoHS-Status | [DATA_NEEDED] | Non-compliant (ceramic CPGA, contains lead) |
| Macro Cells | — | 560 |
| Typical Gates | — | 12,000 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Propagation Delay (tpd) | — | 15 ns (speed grade -15) |
| Propagation Delay (alternate datasheet figure) | — | 16.6 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| Operating Temperature (Commercial) | — | 0C to +70C |
| Package Type | — | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Montageart | — | Through-Hole |
| Programmability | — | In-System Programmable (ISP) via JTAG IEEE 1149.1 |
| Lebenszyklusstatus | — | Obsolete (legacy Altera MAX 9000 family) |