EPM9560RC208-10 vs EPM9480RC208-15 Vergleich

Detaillierter Direktvergleich von EPM9560RC208-10 von Intel und EPM9480RC208-15 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM9560RC208-10 EPM9480RC208-15
Marke Intel Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $15,40 $24,95
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 560 —
Logic Array Blocks (LABs) 16 —
Maximum User I/O Pins 212 (208-pin package variant) —
Usable Gates 12,000 10,000 gates
Pin-to-Pin Delay (tPD) 10 ns —
Maximum Frequency (fMAX) [DATA_NEEDED: internal toggle frequency in MHz] —
Supply Voltage (VCCINT) 5.0 V —
I/O Standards Supported 5.0 V TTL, 3.3 V LVTTL, 2.5 V (multiVolt I/O) —
Configuration Memory EEPROM (in-system programmable via JTAG) EEPROM (non-volatile)
Process Technology 0.30 µm CMOS EEPROM —
Betriebstemperatur 0C to +70C (commercial) -40C to +85C (commercial)
Gehäuse 208-pin RQFP (Plastic Quad Flat Pack) RQFP-208
Montageart Surface Mount Surface Mount
Lead-Free [DATA_NEEDED: confirm lead-free status -10 suffix is conventional Pb-containing] —
RoHS-Status [DATA_NEEDED: not stated in retrieved distributor listings] [DATA_NEEDED: RoHS compliance status]
Programmability JTAG (IEEE 1149.1) in-system programming In-System (ISP) via JTAG IEEE 1149.1
Logic Cells / Macro Cells — 480 macro cells
Maximum Operating Frequency — 117.6 MHz
Propagation Delay (tPD) — 15 ns
User I/O Pins — 153
Versorgungsspannung — 5.0 V
Architecture — Multiple Array MatriX (MAX) - 3rd generation
MSL-Level — [DATA_NEEDED: MSL rating]

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